1. Field of the Invention
The invention relates to electrostatic discharge protection and, in particular, to an electrostatic discharge protection device applied in high voltage input/output (I/O).
2. Description of the Related Art
FIGS. 1A and 1B respectively show a layout and a cross section of a conventional double diffused drain (DDD) N-type metal oxide semiconductor (NMOS) device acting as an electrostatic discharge (ESD) protection device applied in high voltage input/output (I/O). The NMOS device comprises a poly gate 101 with multiple fingers, an N-type double diffused drain region 103, an N-type drain region 105, and two N-type source regions 107. The multiple fingers are mutually connected in parallel over a P-type substrate or active region 109 and together form the poly gate 101. The N-type double diffused drain region 103 is disposed in the P-type substrate or active region 109 and located between the two fingers of the poly gate 101. The N-type double diffused drain region 105 is disposed in the N-type double diffused drain region 103. The N-type source regions 107 are disposed in the substrate or active region 109 and on two sides of the poly gate 101.
In FIG. 1B, P-type guard rings are connected to a low voltage potential (Vss) such that the P-type substrate or active region 109 is biased at the low voltage potential and junctions between the N-type source regions 107 and the P-type substrate or active region 109 are not forward biased. The N-type source regions 107 are also connected to the low voltage potential (Vss). As shown in FIG. 1B, a parasitic bipolar junction transistor (BJT) is formed in the NMOS device. The N-type source regions 107, the P-type substrate or active region 109, and the N-type double diffused drain respectively act as emitters, bases, and collectors of the parasitic BJT. When the N-type drain region 105 is subject to an ESD pulse, the parasitic BJT is instantly turned on and a large ESD current is discharged through the NMOS device.